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10.1109/SIU49456.2020.9302370

Yazıcı, F., Yıldız, A. S., Yazar, A., & Schmidt, E. G. (2020). An On-chip Switch Architecture for Hardware Accelerated Cloud Computing Systems. In 2020 28th Signal Processing and Communications Applications Conference (SIU) (pp. 1-4). IEEE.

@inproceedings{yazici2020onchip,
  title={An On-chip Switch Architecture for Hardware Accelerated Cloud Computing Systems},
  author={Yaz{\i}c{\i}, Fatih and Y{\i}ld{\i}z, Ayhan Sefa and Yazar, Alper and Schmidt, Ece G{\"u}ran},
  booktitle={2020 28th Signal Processing and Communications Applications Conference (SIU)},
  pages={1--4},
  year={2020},
  organization={IEEE}
}

Abstract

In this paper, we propose a scalable on-chip packet switch architecture for hardware accelerated cloud computing systems. Our proposed switch architecture is implemented on the FPGA and interconnects reconfigurable regions, 40 Gbps Ethernet interfaces and a PCIe interface. The switch fabric operates at line speed to achieve scalability. We propose a new algorithm that grants access to the fabric according to the allocated prioritization to input-output port pairs. The switch is implemented on Xilinx Zynq 7000-SoC and can work at 40 Gbps rate. Our simulation results show that our proposed algorithm achieves desired prioritization without degrading the throughput.

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